A half adder is a logical circuit that performs an addition operation on two one-bit binary numbers often written as A and B. The half adder output is a sum of the two inputs usually represented with the signals C_{out} and S where sum=2*Cout+S. Following is the logic table for a half adder:
Inputs | Outputs | ||
A | B | C | S |
0 | 0 | 0 | 0 |
0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 |
1 | 1 | 1 | 0 |
Example half adder circuit diagram
As an example, a Half Adder can be built with an XOR gate and an AND gate.
___________
A ------| |
| Half |----- S=A(+)B
| Adder |
| |----- C=A.B
B ------|___________|
Full adder:
Schematic symbol for a 1-bit full adder with C_{in} and C_{out} drawn on sides of block to emphasize their use in a multi-bit adder.
A full adder is a logical circuit that performs an addition operation on three one-bit binary numbers often written as A, B, and C_{in}. The full adder produces a two-bit output sum typically represented with the signals C_{out} and S where sum=2*Cout+S. The full adder's truth table is:
Inputs | Outputs | |||
A | B | C_{i} | C_{o} | S |
0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 1 |
0 | 1 | 0 | 0 | 1 |
1 | 1 | 0 | 1 | 0 |
0 | 0 | 1 | 0 | 1 |
1 | 0 | 1 | 1 | 0 |
0 | 1 | 1 | 1 | 0 |
1 | 1 | 1 | 1 | 1 |
A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with S=(A(+)B)(+)Cin and Cout=(A.B)+(Cin.(A(+)B)).
Example full adder circuit diagram
Inputs: {A, B, Cin} → Outputs: {S, Cout}
Example full adder circuit diagram using only NAND and XOR gates
Inputs: {A, B, Cin} → Outputs: {S, Cout}
In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip.
A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting C_{i} to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and C_{i}, and C_{o} could be made the three-bit majority function of A, B, and C_{i}.
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