As in any combinational ckt, the signal must propagate through the gates before the correct output sum is available in the output terminals.

A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel. It consists of full adders connected in cascade, with the output carry from one full adder connected to the input carry of the next full adder.

Figure shows the interconnection of 4 full adder (FA) ckts to provide a 4 - bit binary parallel adder. The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 1 denoting the low order bit. The carries are connected in a chain through the full adders. The input carry to the adder is C_{1} and the output carry is C_{5}. The S outputs generate the required sum bits. When the 4 bit full adder ckt is enclosed within an IC package, it has four terminals for the augend bits, four terminals for the addend bits, four terminals for the sum bits, and two terminals for the input and output carries.

Hi there,

ReplyDeleteJust wondering how do u determine the worst-case propagation

delay for your combinational multiplier. You can assume that the delay through every full adder is tpd.

Regards,

Susie

For example, when u do a multiplication of 2 4-bit binary numbers.

ReplyDeleteand I am not so sure when u say 'four terminals for the augend bits, four terminals for the addend bits, four terminals for the sum bits, and two terminals for the input and output carries.'

ReplyDeleteCan u give a bit explanations for these as well?

All the others are explained really clear.

Many thanks