![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg1AhyE210HvUhbIvi50fvtTaRNRTJ9kkrFruzf0A7o4gZnPzUNnS3pRcFaAr53Ula4UHe66wC0kYVCMAIkiWh4D1KuiEM5_6uvyeekm5Uekd73YnpTcGpUvyNlQ4A61hyphenhyphenSuK4GI4qfhw/s400/Block+Diagram+JK+Flick+Flok.gif)
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If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. It can also act as a T flip-flop to accomplish toggling action if J and K are tied together. This toggle application finds extensive use in binary counters.
J-K Flip-Flop Structure:
A simplified version of the versatile J-K flip-flop. Note that the outputs feed back to the enabling NAND gates. This is what gives the toggling action when J=K=1.
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEguFkoXa9EvHwpWbG9jbSpXK6GKzNNZpXNbCyFQaXRg-5uJBHnu1uW1MwmPU_hsM4-gFHYe9eyvudy2PuRH2zN4uq_uf7syia5vI8DHIdyMpR4vKwJEnLiagEQmUtEyipCrh22qOA8k5g/s400/Logic+Diagram+JK+Flick+Flok.gif)
Switching : J-K Flip-Flop:
The positive going transition (PGT) of the clock enables the switching of the output Q. The "enable" condition does not persist through the entire positive phase of the clock. The J & K inputs alone cannot cause a transition, but their values at the time of the PGT determine the output according to the truth table. This is an application of the versatile J-K flip-flop.
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiATyP3vbt7JRbnmzqc9QHqCBTVFAHtsrffj1ntEEWhpKvlaGpuXLCS3cjuuqJjp24UxU2jqhSR7C35TEHMm7bK93pwkeT-WmLXMVyH_Wj3NPb4oy8Zd9YRrZZJNnzy6gvD3hlIX4mI0w/s400/Switching+Diagram+J-K+Flip-Flop.gif)
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